i i i i i pem pem pem pem pem 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram AS8S512K32PEC AS8S512K32PEC rev. 0.1 01/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 austin semiconductor, inc. 16mb, 512kx32 cmos 5.0v, high speed static ram integrated plastic encapsulated microcircuit features ? integrated real-time memory array solution ? no latency or refresh fycles ? parallel read/write interface ? user configurable via multiple enables ? random access memory array ? fast access times: 12, 15, 20, and 25ns ? ttl compatible i/o ? fully static, no clocks ? surface mount package ? 68 lead plcc, no. 99 jedec m0-47ae ? small footprint, 0.990 sq. in. ? multiple ground pins for maximum noise immunity ? single +5v (5%) supply operation description the as8s512k32 is a high speed, 5v, 16mb sram. the device is available with access times of 12, 15, 20 and 25ns creating a zero wait state/latency, real-time memory solution. the high speed, 5v supply voltage and control lines,make the device ideal for all your real-time computer memory requirements. the device can be configured as a 512k x 32 and used to create a single chip external data /program memory array solution or via use of the individual chip enable lines, be reconfigured as a 1m x 16 or 2m x 8. the device provides a 50+% space savings when compared to four 512k x 8, 36 pin sojs. in addition the as8s512k32 has only a 20pf load on the addr. lines vs. ~30pf for four plastic sojs. pin configurations and block diagram 10 11 12 13 14 15 16 17 18 19 20 21 22 dq16 a18 a17 e3\ e2\ e1\ e0\ nc vcc nc nc g\ w\ a16 a15 a14 dq15 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 dq17 dq18 60 dq14 59 dq13 dq19 58 dq12 vss 57 v ss dq20 56 dq11 dq21 55 dq10 dq22 54 dq09 dq23 53 dq08 vcc 52 v cc dq24 51 dq07 dq25 50 dq06 dq26 49 dq05 dq27 48 dq04 vss 47 v ss dq28 46 dq03 dq29 45 dq02 dq30 44 dq01 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 dq31 a6 a5 a4 a3 a2 a1 a0 vcc a13 a12 a11 a10 a09 a08 a07 dq00 23 24 25 26 byte control table chip byte enable control e0\ dq0-7 e1\ dq8-15 e2\ dq16-23 e3\ dq24-31 pin names a0 - a18 address inputs e0\ - e3\ chip enables w\ write enables g\ output enable dq0 - dq31 common data input/output vcc power (+5v 10%) vss ground nc no connection a0-a18 g\ w\ e0\ e1\ dq0-dq7 e2\ dq8-dq15 e3\ dq16-dq23 dq24-dq31 512k x 32 memory array 19
i i i i i pem pem pem pem pem 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram AS8S512K32PEC AS8S512K32PEC rev. 0.1 01/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 austin semiconductor, inc. absolute maximum ratings* voltage on any pin relative to vss -0.5v to 7.0v operating temperature t a (ambient) commercial 0 o c to +70 o c industrial -40 o c to +85 o c storage temperature, plastic -55 o c to +125 o c power dissipation 5.0 watts output current 20 ma junction temperature, tj 175 o c *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those in di cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended dc operating conditions paramete r sym min typ max units supply voltage v cc 4.75 5 5.25 v supply voltage v ss 000v input high voltage v ih 2.2 --- vcc+0.5v v input low voltage v il -0.3 --- 0.8 v ac test conditions input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 2 note: for t ehqz , t ghqz and t wlqz , cl=5pf fig. 2 fig. 3 vcc vcc 480 480 q q 30pf 255 5pf 255 dc electrical characteristics units 12/15 20/25 ns operating power supply current i cc1 w#=v il , i i/o =0ma, min cycle 350 300 ma standby (ttl) power supply current i cc2 e# ? v ih , v in ? v il or v in ? v ih , f=0mhz 120 125 ma full standby power supply current e# ? v cc -0.2v cmos v in ? v cc -0.2v or v in ? 0.2v input leakage current i li v in =0v to v cc a output leakage current i lo v i/o =0v to v cc a ouput high voltage v oh i oh =-4.0ma 2.4 v output low voltage v ol i ol =8.0ma v 0.4 ma 5 5 parameter i cc3 20 20 max min conditions sym truth table g# e# w# mode output power i cc2 i cc3 h l h output deselect high z i cc1 l l h read d out i cc1 x l l write d in i cc1 high z x h x standby capacitance (f=1.0mhz, v in =v cc or v ss ) paramete r sym max unit address lines ci 20 pf data lines cd/q 7 pf write & output enable line w#, g# 20 pf chip enable line e0#, e3# 7 pf
i i i i i pem pem pem pem pem 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram AS8S512K32PEC AS8S512K32PEC rev. 0.1 01/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 austin semiconductor, inc. ac characteristics read cycle jedec alt. min max min max min max min max read cycle time t avav t rc 12 15 20 25 ns address access time t avqv t aa 12 15 20 25 ns chip enable access t elqv t acs 12 15 20 25 ns chip enable to output in low z t elqx t clz 3333ns chip disable to output in high z t ehqz t chz 6799ns output hold from address change t avqx t oh 3333ns output enable to output valid t glqv t oe 6799ns output enable to output in low z t glqx t olz 0000ns output enable to output in high z t ghqz t ohz 6799ns 25ns units parameter symbol 12ns 15ns 20ns read cycle 1 - w \ high, g \ , e \ low address 1 address 2 t avav data 1 data 2 t avqv t avqx a q read cycle 2 - w \ high t ghqz t elqv t elqx e# g# q t ehqz a t avav t glqv t glqx t avqv
i i i i i pem pem pem pem pem 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram AS8S512K32PEC AS8S512K32PEC rev. 0.1 01/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 austin semiconductor, inc. ac characteristics read cycle jedec a lt. min max min max min max min max write cycle time t avav t wc 12 15 20 25 ns chip enable to end of write t elwh t cw 8 101112ns t eleh t cw 8 101112ns address setup time t avwl t as 0000ns t avel t as 0000ns address valid to end of write t avwh t aw 8 101112ns t aveh t aw 8 101112ns write pulse width t wlwh t wp 8 101112ns t eleh t wp 10 12 13 14 write recovery time t whaz t wr 0000ns t ehaz t wr 0000 data hold time t whdx t dh 0000ns t ehdz t dh 0000 write to output in high z t wlqz t whz 06070809ns data to write time t dvwh t dw 6789ns t dveh t dw 6789 output active from end of write t whqx t wlz 3333 25ns units parameter symbol 12ns 15ns 20ns write cycle 1 - w \ controlled e \ a t avav t elwh t avwh t wlwh t avwl t whax w \ high z data valid t wlqz t whqx t dvwh t whdx q d
i i i i i pem pem pem pem pem 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram AS8S512K32PEC AS8S512K32PEC rev. 0.1 01/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 austin semiconductor, inc. write cycle 2 - e \ con trolled a t avel t avav t eleh e \ t aveh t ehax w \ t wleh t ehdx t dveh data valid d high z q package drawing package no. 99 68 l ead p l cc j ede c mo-47 ae 0 .99 5 0 .9 5 6 ma x ma x 0 .9 5 6 ma x 0 .99 5 ma x ma x ma x 0 . 0 4 0 ma x 0 . 050 bs c 0 . 020 0 . 015 0 .9 30 0 .89 0 0 . 1 8 0 0 . 115
i i i i i pem pem pem pem pem 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram AS8S512K32PEC AS8S512K32PEC rev. 0.1 01/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 austin semiconductor, inc. ordering information part numbe r access speed device grade a vailabilit y AS8S512K32PEC-ms na mechanical sample september 2006 AS8S512K32PEC-es na engineering sample october 2006 AS8S512K32PEC-12/it 12ns industrial november 2006 AS8S512K32PEC-15/it 15ns industrial november 2006 AS8S512K32PEC-20/it 20ns industrial november 2006 AS8S512K32PEC-25/it 25ns industrial november 2006 AS8S512K32PEC-12/et 12ns enhanced november 2006 AS8S512K32PEC-15/et 15ns enhanced november 2006 AS8S512K32PEC-20/et 20ns enhanced november 2006 AS8S512K32PEC-25/et 25ns enhanced november 2006 AS8S512K32PEC-12/xt 12ns mil-temp cf AS8S512K32PEC-15/xt 15ns mil-temp november 2006 AS8S512K32PEC-20/xt 20ns mil-temp november 2006 AS8S512K32PEC-25/xt 25ns mil-temp november 2006 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 austin semiconductor 17 68 - ld. plcc 53 [jedec mo-47ae] 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 dq12 dq13 dq06 dq07 vcc dq08 dq03 vss dq14 dq09 dq10 dq11 vss dq04 dq05 dq02 dq01 dq01 dq02 dq05 dq04 vss dq03 dq08 vcc dq07 dq06 vss dq11 dq10 dq09 dq14 dq14 dq13 dq12 dq11 vss dq12 dq13 vcc dq08 dq09 dq10 dq04 dq05 dq06 dq07 dq01 dq02 dq03 vss dq16 dq15 dq16 a18 a17 e3\ e2\ e1\ e0\ a20 a14 nc g\ nc nc g\ w\ a16 a15 a14 nc w\ a16 a15 nc vcc nc nc e3\ e2\ e1\ e0\ nc vcc a19 g\ dq15 dq16 a18 a17 e3\ e2\ e1\ e0\ dq15 dq17 dq18 dq19 w\ a16 a15 a14 vcc nc vss dq20 dq21 dq22 dq23 vcc dq24 dq25 dq26 dq27 vss dq28 dq29 dq30 dq17 dq17 dq18 dq19 vss dq20 dq21 dq22 dq23 vcc dq24 dq25 dq26 dq27 vss dq18 dq19 vss dq20 dq21 dq22 dq23 vcc dq24 dq25 dq26 dq27 vss dq28 dq29 dq30 dq28 dq29 dq30 dq31 a6 a5 a4 a3 a2 a1 a0 vcc a13 a12 a11 a10 a09 a08 a07 dq00 dq31 a6 a5 a4 a3 a2 a1 a0 vcc a13 a12 a11 a10 a09 a08 a07 dq00 dq31 a6 a5 a4 a3 a2 a1 a0 vcc a13 a12 a11 dq00 a10 a09 a08 a07 4mb-sram, 128k x 32: 5.0v = as8s128k32pec 16mb-sram, 512k x 32: 5.0v = AS8S512K32PEC 3.3v = as8slc512k32pec 64mb-sram, 2m x 32: 3.3v = as8slc2m32pec family pin matrix
i i i i i pem pem pem pem pem 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram 16 mb async sram AS8S512K32PEC AS8S512K32PEC rev. 0.1 01/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 austin semiconductor, inc. document title 16mb, 512k x 32, sram, 5.0v, 0.990?sq. - 68 ld. plcc, multi-chip package [ipem] revision history rev # history release date status 0.0 initial release september 2005 advance 0.1 updated order chart january 2009 advance
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